This invention relates to a test element group (TEG) including a large number of elements connected to each other and a semiconductor device which includes a test element group provided on a semiconductor substrate.
In recent years, together with refinement of elements, the layout dependency of element characteristics has become notable. In addition, a dispersion in element characteristic within a wafer has increased. Such layout dependency and dispersion have become a subject upon circuit fabrication. For example, the layout dependency of a threshold voltage, a current-voltage characteristic and so forth and the wafer in-plane dispersion of MOSFETs have a significant influence on the reliability of semiconductor devices and the yield upon fabrication.
As a method of improving the reliability of semiconductor devices and the yield upon fabrication of semiconductor devices, circuit designing is generally used wherein the layout dependency of an element characteristic and the dispersion in element characteristic on a fabrication line are grasped and permitted. Further, to monitor the layout dependency in element characteristic and the characteristic dispersion on a fabrication line of semiconductor devices and manage the numerical values of them leads to stabilization of the yield of semiconductor devices.
In the past, as a method of measuring the layout dependency of an element characteristic and the dispersion of an element characteristic, a method of evaluating a characteristic of a unit element included in each of a plurality of TEGs provided on a wafer is known. Since the TEG includes an element similar to an actual operation element used in a semiconductor element, by evaluating the TEG, the layout dependency of a characteristic and the characteristic dispersion of actual operation elements in the semiconductor device can be estimated. However, every time the generation advances, the layout is complicated and the amount of data of element characteristics necessary for circuit design increases, and also the number of elements whose evaluation is required increases.
Therefore, in an existing evaluation method where a plurality of TEGs in each of which one or several elements which can be evaluated are incorporated, the area for incorporating a required number of TEGs in a semiconductor chip becomes very great. Therefore, in recent years, a method has been proposed wherein, as seen in FIG. 12, a large number of elements such as D(1, 1), D(1, 2), . . . , D(1, n), D(2, 1), D(2, 2), . . . , D(2, n), . . . are disposed in a matrix to achieve a high installation density of elements and a characteristic of the large number of elements is acquired over a small TEG area. The method is disclosed, in Japanese Patent Laid-Open No. 2007-103946 (hereinafter referred to as Patent Document 1).